By Takuo Kitamura, Shunji Tashiro, Masayuki Inagaki (auth.), Julius T. Tou (eds.)
Information structures technology is advancing in lots of instructions with fast strides. Many assorted principles, methodologies, and strategies were conceived and built for making improvements to the layout of data platforms and for inventing new tools for fixing complicated details difficulties. This quantity, the 7th of a continual sequence on details platforms technological know-how, covers 5 well timed themes that are within the mainstream of present curiosity during this transforming into box. In each one bankruptcy, an try out is made to famil iarize the reader with a few uncomplicated history details at the advances mentioned, in order that this quantity can be used independently or along with the former volumes. The emphasis during this quantity is based upon prognosis for electronic structures, dispensed details networks, micro computing device expertise, and information constructions for development attractiveness. in recent times, electronic structures have came upon common functions in online real-time processing. Such functions call for excessive reliability, availability, and serviceability. Reliability might be greater by utilizing hugely trustworthy elements. development in integrity will be observed via retry operation and redundant configuration. Serviceability might be more advantageous by way of employing fault prognosis options. bankruptcy 1 is dedicated to this significant topic. Fault prognosis thoughts are built to enhance serviceability and to shorten suggest time for fix. Kitamura, Tashiro, and Inagaki speak about many fresh equipment for fault prognosis and clarify them with illustrative examples.
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Extra info for Advances in Information Systems Science: Volume 7
14. FLT concept. clock. The output flip-flop values are scanned out from the output flip-flops and compared with the predetermined correct data in the diagnostic equipment. When comparison result shows no coincidence, a fault is detected. 2. Diagnostic Execution (a) FL T Execution Outline. The IBM 360 FLT(34,35) is shown in Fig. 16, Test data are inserted from a FLT controller, which is independent of CPU, When the load signal is given to the FLT controller, the FLT controller activates the channel and I/O equipment and reads the test patterns into the memory buffer.
In this case, the information that must be propagated to the successor gates is concerned with GI(fr), GI (f2), GI(fl), G I (f5) showing output value 0 differing from output value 1 of Gl · G5Cfr), Gs(fJ, G 5(f1), and G5(f5) are prepared on the memory as information concerning G 5 . After providing input values (Xl X 2 X3 X 4 ) = (1 1 00), the same as the input values of G5 , to the input of each gate, corresponding input values are determined, based on the output values of GICfr), GI (f2), GI(fJ, and GI (f5)' That is, the value of x 1(fr) is replaced from 1 to 0 by GI(fr) = O.
A failed logical unit is logically partitioned into the combinational circuit surrounded by some specified flip-flops. This combinational circuit is called a partition. A partition is a circuit that is constructed from all gates traced successively backward from any given flip-flops until reaching other flip-flops. An example of a partition is shown in Fig. 15. When test data are scanned in, the SCAN IN operation is not applied to all flip-flops in the failed logical equipment, but is applied to input flip-flops in the partition.
Advances in Information Systems Science: Volume 7 by Takuo Kitamura, Shunji Tashiro, Masayuki Inagaki (auth.), Julius T. Tou (eds.)